Decoder for memory data bus

ABSTRACT

Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of U.S. patent application Ser. No.10/411,422, titled FLASH MEMORY DATA BUS FOR SYNCRONOUS BURST READ PAGE,filed Apr. 10, 2003, which is commonly assigned to the assignee of thepresent invention and the entire contents of which are incorporatedherein by reference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to memory devices and inparticular the present invention relates to Flash memory devices withsynchronous burst read modes.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal storage areas in thecomputer. The term memory identifies data storage that comes in the formof integrated circuit chips. There are several different types of memoryused in modern electronics, one common type is RAM (random-accessmemory). RAM is characteristically found in use as main memory in acomputer environment. RAM refers to read and write memory; that is, youcan both write data into RAM and read data from RAM. This is in contrastto ROM, which permits you only to read data. Most RAM is volatile, whichmeans that it requires a steady flow of electricity to maintain itscontents. As soon as the power is turned off, whatever data was in RAMis lost.

Computers almost always contain a small amount of read-only memory (ROM)that holds instructions for starting up the computer. Unlike RAM, ROMcannot be written to. An EEPROM (electrically erasable programmableread-only memory) is a special type non-volatile ROM that can be erasedby exposing it to an electrical charge. EEPROM comprise a large numberof memory cells having electrically isolated gates (floating gates).Data is stored in the memory cells in the form of charge on the floatinggates. Charge is transported to or removed from the floating gates byspecialized programming and erase operations, respectively.

Yet another type of non-volatile memory is a Flash memory. A Flashmemory is a type of EEPROM that can be erased and reprogrammed in blocksinstead of one byte at a time. A typical Flash memory comprises a memoryarray, which includes a large number of memory cells. Each of the memorycells includes a floating gate field-effect transistor capable ofholding a charge. The data in a cell is determined by the presence orabsence of the charge in the floating gate. The cells are usuallygrouped into sections called “erase blocks.” Each of the cells within anerase block can be electrically programmed in a random basis by chargingthe floating gate. The charge can be removed from the floating gate by ablock erase operation, wherein all floating gate memory cells in theerase block are erased in a single operation.

Both RAM and ROM random access memory devices have memory cells that aretypically arranged in an array of rows and columns. During operation, arow (page) is accessed and then memory cells can be randomly accessed onthe page by providing column addresses. This access mode is referred toas page mode access. To read or write to multiple column locations on apage requires the external application of multiple column addresses. Toincrease access time, a burst mode access has been implemented. Theburst mode uses an internal column address counter circuit to generateadditional column addresses. The address counter begins at an externallyprovided address and advances in response to an external clock signal ora column address strobe signal.

Two common types of Flash memory array architectures are the “NAND” and“NOR” architectures, so called for the logical form in which the basicmemory cell configuration arranged in each. In the NOR arrayarchitecture, the floating gate memory cells of the memory array arearranged in a matrix. The gates of each floating gate memory cell of thearray matrix are coupled by rows to word select lines (word lines) andtheir drains are coupled to column bit lines. The source of eachfloating gate memory cell is typically coupled to a common source line.The NOR architecture floating gate memory array is accessed by a rowdecoder activating a row of floating gate memory cells by selecting theword line coupled to their gates. The row of selected memory cells thenplace their stored data values on the column bit lines by flowing adiffering current if in a programmed state or not programmed state fromthe coupled source line to the coupled column bit lines.

A NAND array architecture also arranges its array of floating gatememory cells in a matrix such that the gates of each floating gatememory cell of the array are coupled by rows to word lines. However eachmemory cell is not directly coupled to a source line and a column bitline. Instead, the memory cells of the array are arranged together instrings, typically of 8 to 16 each, where the memory cells in the stringare coupled together in series, source to drain, between a common sourceline and a column bit line. The NAND architecture floating gate memoryarray is then accessed by a row decoder activating a row of floatinggate memory cells by selecting the word select line coupled to theirgates. In addition, the word lines coupled to the gates of theunselected memory cells of each string are also driven. However, theunselected memory cells of each string are typically driven by a highergate voltage so as to operate them as pass transistors and allowing themto pass current in a manner that is unrestricted by their stored datavalues. Current then flows from the source line to the column bit linethrough each floating gate memory cell of the series coupled string,restricted only by the memory cells of each string that are selected tobe read. Thereby placing the current encoded stored data values of therow of selected memory cells on the column bit lines.

A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higherclock speeds than conventional DRAM memory. SDRAM synchronizes itselfwith a CPU's bus and is capable of running at 100 MHZ or 133 MHZ, aboutthree times faster than conventional FPM (Fast Page Mode) RAM, and abouttwice as fast EDO (Extended Data Output) DRAM and BEDO (Burst ExtendedData Output) DRAM. An extended form of SDRAM that can transfer a datavalue on the rising and falling edge of the clock signal is calleddouble data rate SDRAM (DDR SDRAM, or simply, DDR). SDRAM's can beaccessed quickly, but are volatile. Many computer systems are designedto operate using SDRAM, but would benefit from non-volatile memory. Asynchronous Flash memory has been designed that allows for anon-volatile memory device with an SDRAM interface. Although knowledgeof the function and internal structure of a synchronous Flash memory isnot essential to understanding the present invention, a detaileddiscussion is included in U.S. patent application Ser. No. 09/627,682filed Jul. 28, 2000 and titled, “Synchronous Flash Memory.”

Memory devices generally have a minimum read latency time that arequesting device must wait after sending the memory device the row andcolumn address before the data is available to be read. This minimumlatency is typically due to the time required by the sense amplifiers toread the data values from the memory array that has been selected by therow and column address decoders. Additionally, other delay componentsare also incorporated in the minimum read latency. These are typicallydue to such items as the delay of the column address decoding andcoupling the sensed data to the external data lines through the databuffer. As these other delay components are typically small, it iscommon practice to equate the minimum read latency to the minimumsensing time of the sense amplifiers of the memory device.

To minimize read latency for burst accesses and/or subsequent readrequests, which will often occur within the same selected row or column“page”, memory devices will typically sense all the data bits of aselected column page at once. This is generally accomplished byincorporating a large number of sense amplifiers into the memory device,allowing all the data bits of the selected column page to be read inparallel. Because of the large number of sense amplifiers, a large databus is usually also incorporated to couple the sense amplifiers to thememory array and to the internal data buffer of the memory device. Thelarge number of sense amplifiers and large internal data bus to pre-readthe other data words of the column page are particularly important forthe operation of memory devices capable of burst mode access, wheresequentially addressed data words are read from the memory device oneach following clock cycle after the initial request and the readlatency delay.

The large number of sense amplifiers and their coupled internal memorybus can significantly increase the circuit space requirements of thememory device on the integrated circuit substrate that it ismanufactured on. Generally, the larger the space required for anintegrated circuit design the fewer the number of copies of the designcan be placed on a substrate wafer as it is processed and later “diced”into individual “dies,” each die having a single circuit copy on it.This lowers the typical device yield of a substrate wafer, defined asthe number of unflawed devices produced from a substrate wafer, byincreasing the probability of a given device containing a flaw due tothe larger die size. The reduced number of dies that are yielded from asubstrate wafer and the increased odds of any single die containing aflaw have the effect of increasing the production cost of the resultingmemory device.

Additionally, the increased number of simultaneously active senseamplifiers in an individual memory device also increases the amount ofpower consumption of the device by increasing the amount of currentrequired while it is engaged in a read operation. The increased currentconsumption of the memory device increases the inherent level ofelectronic noise that is seen internal to the memory device andexternally in the circuitry that surround it, increasing the probabilityof a noise induced read or logic error. The noise levels of a memorydevice often require the designer to utilize higher voltages to operatethe circuit and mitigate the possibility of such an error, furtherincreasing device power consumption and possible device feature sizes.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foralternative circuits and methods of reading memory arrays that minimizethe number of sense amplifiers and the size of the internal data bus.

SUMMARY

The above-mentioned problems with large numbers of sense amplifiers,their accompanying large internal memory busses, and other problems areaddressed by the present invention and will be understood by reading andstudying the following specification.

The various embodiments relate to memory devices that reduce the numberof sense amplifiers and internal data bus required for read operationswhile enabling burst mode operation. Memory device embodiments of thepresent invention utilize a reduced number of sense amplifiers to sensethe data bits of the selected column page. This is accomplished bymultiplexing the sense amplifiers and latching the results to allow thesense amplifiers to sense the next set of data lines from the selectedcolumn page. The reduced number of sense amplifiers allows for a smallerinternal data bus to be utilized, saving additional circuit space androuting resources. The number of sense amplifiers are chosen such thatthe resulting number of data words they read are equal to or greaterthan the greatest number of data words that can be read from the memorydevice in the time of the minimum read latency time/sensing cycle timeof the sense amplifiers. This allows the memory to be able to sense thenext set of data bit lines and assemble the data words before they arerequired to be available for reading out of the memory device. Aspecialized decoder, called a domino decoder, and a control circuit areutilized to select a set of data bit lines to be sensed and control thedata latches. This allows there to be no gaps or latencies while readingdata from the memory due to reloading the read latches or inmultiplexing the sense amplifiers to sense a following set of data bitlines in the selected column page. Additionally, this allows a burstread starting point to be selected at random from the selected columnpage.

For one embodiment, the invention provides a method of operating amemory device comprising latching a first set of data words, readingdata words from the first set of data words while sensing a second setof data words, latching a first portion of the second set of data wordswhile reading a last word of the first set of data words, and latching asecond portion of the second set of data words after reading the lastword of the first set of data words.

In another embodiment, the invention provides a method of operating amemory device comprising receiving an address, having a row address, acolumn address, and an initial data word offset address, selecting acolumn page with the address from a memory array having a plurality ofmemory cells, dividing the column page into a plurality of data wordsets based on the offset address, wherein each data word set contains anequal number of one or more data words, selecting and sensing an initialdata word set of the column page, wherein the initial data word setbegins with the data word of the data word offset address, selecting andsensing a following sequential data word set of the column page whilereading the individual data words of the initial data word setsequentially from the memory device, and selecting and sensing anyfurther following sequential data word sets of the column page whilereading the individual data words of a previously sensed data word setsequentially from the memory device until all the data word sets of theselected column page have been read.

In yet another embodiment, the invention provides a memory device havinga memory array having a plurality of memory cells arranged in rows andcolumns, an address circuit, adapted to receive a memory address, a rowdecoder coupled to the address latch circuit and the memory array,wherein the row decoder is adapted to access a selected row page ofmemory from the memory array, a column decoder coupled to the addresslatch circuit and the memory array, wherein the column decoder isadapted to access a selected column page having a number of bitlinesfrom the memory array, a decoder circuit coupled to the address circuit,wherein the decoder circuit is adapted to select a set of data wordsfrom the selected column page, each data word having a plurality ofbitlines, a multiplexer coupled to the decoder circuit, a plurality ofsense amplifiers, wherein the multiplexer is adapted to selectivelycouple the plurality of bitlines of each data word of the selected setof data words to the plurality of sense amplifiers, and wherein thenumber of bitlines of the selected column page is greater than thenumber of the plurality of sense amplifiers, an intermediate latchcircuit having a plurality of data word latch groups coupled to thesense amplifiers, an intermediate latch control circuit coupled to theintermediate latch control circuit, wherein the intermediate latchcontrol circuit is adapted to clock the intermediate latches to latch ina first set of data words, and wherein the intermediate latch circuit isadapted to latch in a new data word set while a final data word is readfrom a current data word set held in the intermediate data latch circuitin a multiple trigger latching action, such that there are no gaps inreading the final data word of the current data word set and a firstdata word of the new data word set.

In a further embodiment, the invention provides a method of operating alatch circuit comprising latching a first set of data words, latching afirst portion of a second set of data words while reading a last word ofthe first set of data words, and latching a second portion of the secondset of data words after reading the last word of the first set of datawords.

Further embodiments of the invention include methods and apparatus ofvarying scope.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of a system containing a Flashmemory device.

FIG. 2 is a simplified block diagram of an output stage of a memorydevice of the prior art.

FIG. 3 is a waveform diagram detailing a burst mode operation of amemory device of the prior art.

FIG. 4 is a simplified block diagram of an output stage of a memorydevice in accordance with an embodiment of the present invention.

FIG. 5 is a block diagram of an output stage of a memory device inaccordance with an embodiment of the present invention.

FIG. 6 is a waveform diagram showing a burst mode operation of a memorydevice of an embodiment of the present invention.

FIG. 7 is a diagram of an address latch generator of a memory inaccordance with an embodiment of the present invention.

FIG. 8 is a waveform diagram detailing the signals of an address latchgenerator of an embodiment of the present invention.

FIG. 9 is a diagram of the A1-A4 latches and associated logic of amemory in accordance with an embodiment of the present invention.

FIG. 10 is a waveform diagram detailing the signals of the A1-A4 latchesand associated logic of an embodiment of the present invention.

FIGS. 11A and 11B are diagrams of a domino decoder of a memory inaccordance with an embodiment of the present invention.

FIGS. 12A and 12B are waveform diagrams detailing the signals of adomino decoder of an embodiment of the present invention.

FIG. 13 is a diagram of the read pass, multiplex, sense amplifiers, andintermediate data latches of a memory in accordance with an embodimentof the present invention.

FIG. 14 is a diagram of an intermediate data latch of a memory inaccordance with an embodiment of the present invention.

FIGS. 15A and 15B are diagrams of a sense amplifier enable circuit andits signal waveforms of a memory in accordance with an embodiment of thepresent invention.

FIGS. 16A and 16B are diagrams of a sense amplifier enable one shotcircuit and its signal waveforms of a memory in accordance with anembodiment of the present invention.

FIGS. 17A and 17B are diagrams of a sense amplifier to intermediatelatch transfer circuit and its signal waveforms of a memory inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings that form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims and equivalents thereof.

Conventional memory devices typically have large word decode groups tokeep up with sequential memory accesses or burst data transfers, thuseach request initiates a large number of data words being decoded andsensed at once. This requires a large number of sense amplifiers (256 ormore are commonly used) and a correspondingly large internal data bus toread and transfer the selected word decode group to the data I/O bufferin parallel. Memory devices incorporating embodiments of the presentinvention utilize a reduced number of sense amplifiers to sense the databits of the selected column page. This is accomplished by multiplexingthe sense amplifiers and latching the results to allow the senseamplifiers to sense the next set of data lines from the selected columnpage. The reduced number of sense amplifiers allows for a smallerinternal data bus to be utilized, saving additional circuit space androuting resources.

The number of sense amplifiers are chosen such that the resulting numberof data words they read are equal to or greater than the greatest numberof data words that can be read from the memory device in the time of theminimum read latency time/sensing cycle time of the sense amplifiers.This allows the memory to be able to sense the next set of data bitlines and assemble the data words before they are required to beavailable for reading out of the memory device. A specialized decoder,called a domino decoder, and control circuitry is utilized to select aset of data bit lines to be sensed and control the data latches. Thesecircuits allow there to be no gaps or latencies while reading data fromthe memory due to reloading the read latches or in multiplexing thesense amplifiers to sense a following set of data bit lines in theselected column page. Additionally, this allows burst reads startingfrom a point selected at random from the selected column page.

FIG. 1 shows a simplified diagram of a system 128 incorporating a memorydevice of the present invention 100 coupled to a host 102, which istypically a processing device, a processor, or a memory controller. Thememory device 100 is a Flash memory has an address interface 104, acontrol interface 106, and a data interface 108 that are each coupled tothe processing device 102 to allow memory read and write accesses.Internal to the Flash memory device a control state machine 110 directsthe internal operation; managing the Flash memory array 112 and updatingRAM control registers and non-volatile erase block management registers114. The RAM control registers and tables 114 are utilized by thecontrol state machine 110 during operation of the Flash memory 100. TheFlash memory array 112 contains a sequence of memory banks or segments116. Each bank 116 is organized logically into a series of erase blocks(not shown). Memory access addresses are received on the addressinterface 104 of the Flash memory 100 and divided into a row and columnaddress portions. On a read access the row address is latched anddecoded by row decode circuit 120, which selects and activates a rowpage (not shown) of memory cells across a selected memory bank. The bitvalues encoded in the output of the selected row of memory cells arecoupled from a local bitline (not shown) to a global bitline (not shown)and detected by sense amplifiers 122 associated with the memory bank.The column address of the access is latched and decoded by the columndecode circuit 124. The output of the column decode circuit selects thedesired column data from the internal data bus (not shown) that iscoupled to the outputs of the individual read sense amplifiers 122 andcouples them to the data buffer 126 for transfer from the memory devicethrough the data interface 108. On a write access the row decode circuit120 selects the row page and column decode circuit selects write senseamplifiers 122. Data values to be written are coupled from the databuffer 126 via the internal data bus to the write sense amplifiers 122selected by the column decode circuit 124 and written to the selectedfloating gate memory cells (not shown) of the memory array 112. Thewritten cells are then reselected by the row and column decode circuits120, 124 and sense amplifiers 122 so that they can be read to verifythat the correct values have been programmed into the selected memorycells.

FIG. 2 shows a simplified block diagram of a Flash memory 200 of theprior art detailing the read output stage. In FIG. 2, an address requestis received by the Flash memory device 200 on the address input pads202, 204 and is buffered. The address request is latched into theaddress latches 206 by the address valid latch signal 208, which isgenerated by the address latch generator circuit 210 from the addressvalid input signal 212 and clock signal input 214. The address isdecoded by the row decoder (not shown) and activates a row of floatinggate memory cells of the memory array (not shown), which put their datavalues on the column bit lines 218. The column page decoder 216 selects16 data words of 16 bits each from the bit lines 218 with the Y-passgates 220 and couples them to 256 sense amplifiers 228 grouped in dataword groups of 16 each. There are typically a large number of senseamplifiers 228 (generally >=256 in each bank) such that each selectedbitline is associated with an individual sense amplifier 228. The senseamplifiers 228 are enabled to begin sensing by the sense amplifierenable signal 226 which is generated by the sense amplifier enablecircuit 224. The sense amplifier enable circuit 224 is in turn triggeredby the address valid one shot circuit 222 that is coupled to the addressvalid signal line 208.

A latency counter 230 is utilized to delay access to the data valueoutputs of the sense amplifiers 228 until the minimum read delay/sensingcycle time has passed and the data values are available at the senseamplifier 228 outputs. The latency counter 230 is loaded with an initialvalue from the read configure register (RCR) 232 and is clocked by aninternal clock signal 234 generated by address latch generator circuit210 from the clock signal input 214. When the configured latency timehas passed, the latency counter 230 outputs a latency timeout signal236, which activates the clock transmission gate 238 and couples theinternal clock signal 234 to a 4-bit address counter 242 through a oneclock delay 240. The 4-bit address counter 242 is loaded with an initialvalue/address from the lowest 4 address inputs 204, coupled from theaddress latches 206. The address value contained in the 4-bit addresscounter 242 is coupled to a 16 data word decoder 244. The 16 data worddecoder 244 is also coupled to and activated by the latency counter 230via latency timeout signal line 236. When the latency counter 230expires, the 16 data word decoder utilizes the address outputs of the4-bit address counter 242 to activate one of 16 read word select signals(RW1-RW16) 250. The activated read word select signal 250 selects theoutputs of one group of 16 sense amplifiers via the data wordtransmission gates 246 and places one of the 16-bit data words on theinput/output data buffers (I/O buffers) 248 to be read from the Flashmemory device 200.

After expiration of the latency timer and the starting of data transferfrom the Flash memory device 200, the next clock signal pulse (or nextclock pulse transition/edge if a dual data rate memory) arriving at theclock input 214 increments the 4-bit address counter 242 and its currentaddress value, advancing it to the next sequential address. This causesthe coupled 16 data word decoder 244 to select the next sequential dataword from the sense amplifier outputs of the selected column page andcouple them to the input/output data buffers 248 to be read from theFlash memory device 200. Data words continue to be read in this fashionon every successive clock pulse until the burst read access is ended orthe final data word (data word 16) of the selected column page is read(the address counter reaches 16). When the final data word of a selectedcolumn page is read and the burst access is continued the next columnand/or row page must be selected from the memory array and/or bitlines.This changing of the column and/or row page introduces a delay, whilememory cells are accessed and the minimum latency time has again passedfor the sense amplifiers to read the new column page, until the accessis allowed to continue.

FIG. 3 shows a waveform diagram 300 of a 16 data word burst readoperation with the Flash memory 200 of the prior art detailed in FIG. 2.In the waveform diagram 300, a burst access data request is received atthe memory device 200 that accesses a selected memory row and page. Thememory burst begins at data word 4 of the selected 16 data word columnpage and wraps around in the current column page or continues of thefollowing column page until data word 3. In FIG. 3, the data readrequest is received at the memory device on the address inputs (notshown) and is latched in by a signal on the active low address validinput (ADVpad*) 302. The active signal on the address valid input 302 inturn generates the address valid latch (ADVL) 306 and the address validlatch one shot (ADVLOS) 308 signals. The generation of the ADVL 306signal latches in the address input values into the address latches 206and generates row and column select signals (not shown) and the 16 dataword page select (16WPS) signal 312 from the page decoder circuit 216,selecting the memory cells and coupling their bitlines 218 to the inputsof the sense amplifiers 228. The generation of the ADVLOS 308 signalalso generates the sense amplifier enable signal 310 from the senseamplifier enable circuit 224, causing the sense amplifiers 228 to beginsensing the data values that have been coupled to them. At theexpiration of the latency counter 230, after 7 clock periods 304, thelatency timeout (LT) signal 314 becomes active. The active latencytimeout signal 314 activates the 4-bit address counter 242 and enablesthe 16 word decoder 244. The 4-bit address counter 242 has been loadedwith an initial starting data word value from the lowest four addressvalues from the address latches 206 for data word 4 of the selectedcolumn page and causes the 16 word decoder 244 to output read wordselect 4 (RW4) 316 which couples the output of sense amplifiers 228 fordata word 4 to the data input/output buffer 248 and the data word 4 isread 348 from the memory device 200.

As subsequent clock pulses are received on the clock signal input(CLKpad) 304, the 4-bit address counter 242 is advanced to the next dataword address and causes the 16 word decoder 244 to output the nextsubsequent read word select. Thus, the 4-bit address counter 242, for a16 data word burst will transition on each subsequent clock cycle 304from the initial data word address of 4 to 16 and then roll over tobegin counting from 1 until 3 is reached. In response to its input fromthe 4-bit address counter 242, the 16 word decoder 244 selects in turnRW4 316, RW5 318, RW6 320, RW7 322, RW8 324, RW9 326, RW10 328, RW11330, RW12 332, RW13 334, RW14 336, RW15 338, RW16 340, RW1 342, RW2 344,and RW3 346 causing their associated data values to be sequentiallyoutput 348 from the memory device 200 in a burst read operation onsequential clock cycles 304. In the situation where the burst accesscontinues in the following column page to read data words 1-3, insteadof wrapping around in the current column page to read data words 1-3, agap in the data transfer or “wait state” would be inserted between thereading of data word 16 and data word 1 of the following column page toallow once again for the passage of the minimum latency time.

It is noted that the initial data word access in the above examplestarted at data word 4 of the selected column page and that otherstarting data word accesses and burst sizes are possible and willoperate in a substantially similar manner. It is also noted that burstread operations with other types of memory devices are similar and wouldbe apparent to those skilled in the art.

As stated above, embodiments of the present invention utilize a reducednumber of sense amplifiers to sense the data bits of the selected columnpage. This is accomplished by selecting a smaller initial word group tobe sensed by the reduced set of sense amplifiers from the selectedcolumn page bitlines, latching the results of the current “sensingcycle” from the sense amplifiers, and multiplexing the sense amplifiersto the next un-sensed set of bitlines. This procedure allows the senseamplifiers to sense the next set of un-sensed bitlines/data words sothat they are available before the current set of latched data words areread from the memory device. The smaller data word decode group allowsfor a smaller number of data words to be decoded and sensed in a single“sensing cycle”. The smaller data word decode group in turn allows for asmaller data bus and fewer sense amplifiers in the resulting memory. Thereduction in the internal data bus and number of sense amplifiers allowsfor embodiments of the present invention to reduce the overall memorydevice circuit space/die size. Additionally, embodiments of the presentinvention reduce the current, noise, and power usage of the memorydevice through a reduction in the number of active sense amplifiersduring a read operation.

The reduction in the number of sense amplifiers in memory deviceembodiments of the present invention can be up to 50%-75%, dependent onthe speed of the memory and the minimum latency requirement/sensingcycle time of the underlying memory technology. In embodiments of thepresent invention, the minimum number of sense amplifiers and/or addressbus lines required for a given memory device are typically related asgreater than or equal to the number of bits in the burst divided by thetime required to clock all data words of the burst out of the memorydivided by the sense cycle time {Sense Amp divider=(number of data wordsin burst * clock period)/minimum read latency, Minimum sense amps andbus lines=bits in burst/((number of data words in burst * clockperiod)/minimum read latency)}. To hold previously sensed data wordswhile a multiplexer circuit is utilized to direct the reduced number ofsense amplifiers to new bitlines and the next group of data words areread, embodiments of the present invention utilize intermediate datalatches. A specialized intermediate data latch control circuit isutilized to avoid latency and/or gaps in transitioning from one set ofsensed and latched data words to the next sequential set of data wordsthat have just been sensed.

FIG. 4 shows a simplified block diagram of a memory device 400 of anembodiment of the present invention detailing the output stages. Thememory device 400 has a 256 bitline column page and has a minimumlatency/sense amplifier cycle time such that it allows the senseamplifiers of the memory device 400 to be reduced by at least half, from256 to 128 sense amplifiers. This reduction in sense amplifiers allowsthe internal bus sizes to be reduced from 256 bits to 128 bits andallows the read current, noise, and power levels due to the senseamplifiers and internal data bus to also be reduced.

In FIG. 4, an address request is received by the memory device 400 onthe address input pads 402 (only address inputs A4-A1 shown) and arebuffered. The address request is latched into the address latches 406 bythe address valid latch signal 408, which is generated by the addresslatch logic 410 from the address valid input signal 412 and clock signalinput 414. The address is decoded by the row decoder (not shown) andactivates a row of floating gate memory cells of the memory array (notshown), which put their data values on the column bit lines (not shown).The column page decoder (not shown) selects 16 data words of 16 bitseach (for a total of 256 bits) from the 256 selected bit lines. The 256selected bit lines are divided by the memory device 400 into two groupsof 128 bit lines (8 data words) each 416, 418. Each of the two groups of128 bitlines/8 data words 416, 418 are coupled to two Y-passmultiplexers 420, 422. The first Y-pass multiplexer 422 controls thebitlines 418 for data words 1-8 of the selected 16 data word page andthe second Y-pass multiplexer 420 controls the bitlines 416 for datawords 9-16 of the selected 16 data word page. The Y-pass multiplexers420, 422 selectively couple the bitlines of the two groups of 128bitlines/8 data words 416, 418 to 128 sense amplifiers 426 that arearranged in 8 groups of 16, so that each group of 16 sense amplifiers426 sense a single data word. The Y-pass multiplexers 420, 422selectively couple the bitlines of each data word they control (1-8 or9-16) to a single group of sense amplifiers 426 such that each singlesense amplifier group of the 8 groups has either data words 1/9, 2/10,3/11, 4/12, 5/13, 6/14, 7/15, or 8/16 selectively coupled to it.Intermediate latches 428 are coupled to the sense amplifiers 426 to holdthe results of the most recent sensing cycle, allowing the senseamplifiers 426 to be utilized to sense the next 8 data words to be read.The sense amplifiers 426 contain an internal latch to hold the currentlysensed bitline data value. An 8 to 1 data word decoder 430, thatoperates under control of a 3-bit synchronous address counter 432,couples the currently selected data word from the intermediate latches428 to the data input/output (DIO) buffers 434 to be read from thememory device 400.

During a read operation, the Y-pass multiplexers 420, 422 are operatedby a “domino” decoder 424 to select the data words to be coupled to andread by the sense amplifiers 426 from the bitlines 416, 418 of theselected column page. This is done based on the address values for thestarting data word held in address latches 406 for address inputs A1-A4.For a given starting address the domino decoder 424 operates the Y-passmultiplexers 420, 422 to select only the bitlines 416, 418 for the datawords that will be read, starting from the starting address andincreasing in sequence. For example, if the starting address in theselected column page is data word 4, the bitlines 416, 418 for the datawords that are selected and routed from the Y-pass multiplexers 420, 422are for data words 4, 5, 6, 7, 8, 9, 10, and 11.

Because of the mapping of the data words from the Y-pass multiplexers420, 422 to the sense amplifiers 426, there is no overlap of data wordsto be sensed at the sense amplifiers 426. This is particularly importantwhen the starting data word address means that the 8 selected data wordsto be initially sensed are such that the 8 data words are selected fromboth Y-pass multiplexers 420, 422. For example, with a starting addressof data word 6, the data words 6, 7, and 8 are selected from the lowerY-pass multiplexer 422 and routed to the sense amplifier groups 426 thatare coupled to receive either the data words 6/14, 7/15, and 8/16 fromthe Y-pass multiplexers 420, 422, and the data words 9, 10, 11, 12, and13 are selected from the upper Y-pass multiplexer 420 and routed to thesense amplifier groups 426 that are coupled to receive either the datawords 1/9, 2/10, 3/11, 4/12, and 5/13.

Once the minimum latency time has passed and the sense amplifiers havesensed the currently selected data words, the intermediate latches 428will latch in the data words in from the sense amplifiers 426. Thisfrees the sense amplifiers 426 to be repurposed by the Y-passmultiplexers 420, 422 and the domino decoder 424 and begin sensing thenext sequential set of data words. The selected data words are read fromthe intermediate latches 428 under control of a 3-bit synchronousaddress counter 432 and demultiplexer 430 which together select theindividual data word to be coupled to the data input/output lines 434 tobe read out of the memory device 400 for the current clock period.

To read the next 8 data words, the sense amplifiers 426 are repurposedby the domino decoder 424, typically by inverting the address value heldin address latch A4 406, and couples the next 8 data word bitlines 416,418 of the selected column page from the Y-pass multiplexers 420, 422 tothe sense amplifiers 426 to be read. The domino decoder 424 selects thenext 8 data words to be read in sequentially increasing address orderand then will wrap around to select data words to be sensed from thebeginning of the selected column page in sequential order once all otherhigher addressed data words in the column page have been read. Forexample, for the above example with the starting address of data word 4,after latching in the sensed data words 4, 5, 6, 7, 8, 9, 10, and 11into the intermediate latches 428, the domino decoder 424 couples thebitlines 416, 418 for data words 12, 13, 14, 15, 16, 1, 2, and 3 to thesense amplifiers 426 to begin sensing.

In a burst read operation, the 3-bit synchronous address counter 432 isinitially loaded with the address or “offset” within the column page ofthe starting data word that is held in the address latches 406 forA1-A3. Once the minimum latency time has passed and the intermediatelatches 428 have latched in the data words in from the sense amplifiers426, the synchronous address counter 432, via the output data linedemultiplexer 430, selects the data word held at the starting data wordaddress from the intermediate latches 428 and couples it to the datainputs/outputs 434 to be read from the memory device 400. With eachsubsequent clock pulse received on the clock input 414, the 3-bitsynchronous counter 432 increments and presents the next sequentiallyaddressed data word from the intermediate latches 428 on the datainputs/outputs 434. Additionally, as the synchronous counter 432 is only3-bits in size, it will automatically roll over once it has counted to8, regardless of the starting address, to allow it to address all the 8data words held in the intermediate latches 428. For example, with arequested starting address of data word 4 in the current column page,the synchronous counter 432, after the minimum latency/sensing timedelay, selects data words 4, 5, 6, 7, and 8 from the intermediatelatches 428 and presents them sequentially on every clock cycle to beread from the memory device 400. The 3-bit synchronous address counter432 then rolls over allowing it to select data words 9, 10, and 11 fromthe intermediate latches 428 to be read from the memory device 400.

Once all 8 current data words held in the intermediate latches 428 havebeen read, the sense amplifiers 426 will have completed sensing the next8 data words from the bitlines 416, 418, which have been selected by thedomino decoder 424 and the Y-pass multiplexers 420, 422. The next 8 datawords are then latched into the intermediate latches 428 from the senseamplifiers 426. The 3-bit synchronous counter 432, having rolled over,will have wrapped around to begin from the same initial 3-bit startingaddress value and reads the 8 sequential data words from the memorydevice 400 as above. For example, a 16 data word read burst from thecurrent column page starting at data word 4 would select and sense datawords 4, 5, 6, 7, 8, 9, 10, and 11 during the initial minimum latencytime/sensing cycle. The data words 4, 5, 6, 7, 8, 9, 10, and 11 would belatched in the intermediate latches 428 from the sense amplifiers 426.While data words 4, 5, 6, 7, 8, 9, 10, and 11 are being sequentiallyread from the memory device 400, the domino decoder 424 and senseamplifiers 428 select and sense data words 12, 13, 14, 15, 16, 1, 2, and3. When data words 4, 5, 6, 7, 8, 9, 10, and 11 have been read out ofthe memory device 400, data words 12, 13, 14, 15, 16, 1, 2, and 3 arelatched into the intermediate data latches 428 and sequentially read outof the memory device 400 in turn by the wrapped around 3-bit synchronousaddress counter 432 and demultiplexer 430.

When the memory device 400 reaches the highest addressed data word ofthe current column page it will roll over in the current column page toread the data words addressed before the starting data word address,unless it is configured to cross the column page boundary and the nextcolumn page is accessed for read sensing. When the memory device 400crosses over a column page boundary, the starting data word addressoffset (the original starting word address in the starting column page)is not required because of the boundary crossing, which resets theoffset to zero. This allows the domino decoder 424 to select a singlepair of bitlines/Y-pass multiplexers (bitlines/multiplexer set 416 and420, or 418 or 422) starting the lower 8 data words(bitlines/multiplexer set 418 and 422) of the next column page so that acontiguous set of 8 data words to be sensed. Additionally, the 3-bitsynchronous address counter 432 can be reset to an initial startingaddress/offset of zero.

In one embodiment of the present invention, multiple latchingevents/clocks are utilized in latching the data into the intermediatelatches to avoid gaps and/or wait states in the read burst as theintermediate latches are changed from the initial set of 8 sensed datawords to the second. For example, in the memory device of FIG. 4, asingle latch event/clock is used to latch in the data for the initialset of 8 data words that are sensed. When the 8^(th) sequential dataword of the initial set is being read from the data inputs/outputs 434of the memory device 400, the intermediate latches 428 containing thefirst 7 data words are clocked to latch in the first 7 data words of thenext 8 data word set. Once the 8^(th) data word of the set has been readand the synchronous address counter 432 is accessing the 1^(st) dataword of the second 8 data word set, the intermediate latches 428 forfinal 7 data words of the second 8 data word set are clocked to latch inthe new 8^(th) data word of the set. Alternatively, only theintermediate latch 428 containing the 8^(th) data word can be clocked tolatch in the new 8^(th) data word of the second set of 8 data words.This “stuttered” latching for following sets of sensed data words allowsburst read operations to continue without a clock/time gap in the readsequence from the memory device 400 as the following set of 8 senseddata words are latched into the intermediate latches. It is noted thatother similar manners of latching to avoid time gaps/wait states arepossible and should be apparent to those skilled in the art with thebenefit of the present invention.

It is noted that other configuration of the embodiment of the presentinvention described of FIG. 4 incorporating different numbers and sizesof data words, Y-pass multiplexers 420, 422, synchronous addresscounters 432, sense amplifiers 426, and intermediate latches arepossible and should be apparent to those skilled in the art with thebenefit of the present disclosure.

FIG. 5 shows a simplified block diagram of a Flash memory 500 of anotherembodiment of the present invention. In FIG. 5, a Flash memory 500 withburst read capability has a selected column page of 256 bitlines 518coupled to a reduced set of 128 sense amplifiers 526 under control of adomino decoder 524. In operation, the Flash memory device 500 receivesan address request on the buffered address input pads 502, 504. Theaddress request is latched into the address latches 506 and 588 by theaddress valid latch signal 508, which is generated by the address latchgenerator circuit 510 from the address valid input signal 512 and clocksignal input 514. The address is decoded by the row decoder (not shown)and activates a row of floating gate memory cells of the memory array(not shown). The selected row of floating gate memory cells put theirdata values on the column bit lines 518. The column page decoder 546selects 16 data words of 16 bits each (for 256 total bitlines) from thebit lines 518 of the selected row of floating gate memory cells with theY-pass gates 550 and couples them to Y-pass multiplexer transmissiongates 520 that are controlled by a domino decoder 524. The dominodecoder 524 selectively couples 128 bitlines dependant on the receivedaddress from the transmission gates 520 to 128 sense amplifiers 526. Thesense amplifiers 526 are enabled to begin sensing the coupled bitlinesby the sense amplifier enable signal 556, which is generated by thesense amplifier enable circuit 554. The sense amplifier enable circuit554 is in turn triggered by the address valid latch one shot circuit552, the latency counter 560, and the latency counter one shot circuit578. The address valid latch one shot circuit 552 is coupled to andtriggered by the address valid latch signal line 508, producing a pulseon the falling edge of the address valid latch signal 508.

The latency counter/timer 560 is utilized to delay access to the datavalue outputs of the sense amplifiers 526 until the minimum readdelay/sensing cycle time has passed and the data values are available.It is loaded with an initial value from the read configure register(RCR) 562. The latency counter 560 is clocked by an internal clocksignal 564 generated by address latch generator circuit 510 from theclock signal input 514. When the configured latency time has passed, thelatency counter 560 outputs a latency timeout signal 566.

The latency timeout signal 566 triggers the latching of the sensed datafrom the sense amplifiers 526 into intermediate latches 528 andactivates an 8 data word decoder 530 to begin data transfers from thememory device 500. The 8 data word decoder utilizes the address outputsof the 3-bit address counter 532, which has been loaded with an initialvalue/address from the lowest 3 address inputs 504, coupled from theaddress latches 588, to activate one of 8 read word select signals(RW1-RW8) 596. The activated read word select signal 596 selects theoutputs of one group of 8 sense amplifiers via the data wordtransmission gates 576 and places one of the 8 16-bit data words on theinput/output data buffers (I/O buffers) 534 to be read from the Flashmemory device 500.

For burst mode operation the latency timeout signal 566 also activates aclock transmission gate 568, which couples the internal clock signal 564to the 3-bit address counter 542 through a one clock delay 570. When thenext clock signal pulse (or next clock pulse transition/edge if a dualdata rate memory) arrives at the clock input 514, the 3-bit addresscounter 532 increments the current address value and advances to thenext sequential address. This causes the coupled 8 data word decoder 530to select the next sequential data word from the intermediate latches528 and couple it to the input/output data buffers 534 to be read fromthe Flash memory device 500. Data words then continue to be read in thisfashion on every successive clock pulse until the burst read access isended or the final data word of the current latched data word set isread (the address counter rolls over and returns to its initial 3-bitstarting value) and the next set of 8 data words of the 16 data word/256bitline selected column page 516 are latched into the intermediate latch528 for the read burst operation to continue. While the 8current/initial data words are being read out of the memory device 500,the remaining/next set of 8 data words of the 16 data word/256 bitlineselected column page 516 are being sensed so that they will be availableto be latched into the intermediate latches 528 when required. When thefinal data word of a selected column page is read and the burst accessis continued into the next column and/or row page, a delay isintroduced, while the memory cells are selected from the memory arrayand/or bitlines are accessed and the minimum latency time is passed forthe sense amplifiers to read the new column page, until the burst accessis allowed to continue.

In the memory device 500 of FIG. 5, multiple latching events/clocks thatare generated by the intermediate latch control circuit 590 are utilizedin latching the data words from the sense amplifiers 526 into theintermediate latches 528. These multiple latching events/clocks aregenerated on the latch control lines (TW1-TW8) 598 so as to avoid gapsand/or wait states in the read burst as the data words in theintermediate latches 528 are changed from the initial set of 8 senseddata words to the second set. For example, a single latch event/clock isgenerated by the intermediate latch control circuit 590 on all latchcontrol lines (TW1-TW8) 598 is used to latch in the data for the initialset of 8 data words that are sensed. When the 8^(th) sequential dataword of the initial set is being read from the data inputs/outputs 534of the memory device 500, the intermediate latches 528 of all but thecurrently selected/being read data word (the 7 data words already read)are clocked by the intermediate latch control circuit 590 to latch inthe first 7 data words of the next 8 data word set. Once the 8^(th) dataword of the first set has been read and the synchronous address counter532 is accessing the 1^(st) data word of the second 8 data word set, theintermediate latch control circuit 590 clocks the intermediate latches528 for final 7 data words of the second 8 data word set to latch in thenew 8^(th) data word of the set.

The intermediate latch control circuit 590 is in turn controlled by thesense amplifier enable one shot signal 584, a first trigger signal 592,and a second trigger signal 594 from a clock decrement circuit 586. Thesense amplifier enable one shot circuit 582 is coupled to theintermediate latch control circuit 590 and is triggered by the senseamplifier enable signal 556 and the latency timeout signal 566. Theclock decrement circuit 586 is controlled by a clock signal produced bythe clock gate 568 when it is activated by the latency timeout signal566. The clock decrement circuit 586 produces a first trigger signal 592a selected number of clocks after it is activated by the clock signalfrom the clock gate 568. A second trigger signal 594 is then producedfrom the clock decrement circuit 586 one clock pulse later to facilitatelatching of the second set of data words into the intermediate latches528 by the intermediate latch control circuit 590.

The latency timeout signal 566 also initiates the selection and sensingof the second set of data words by the domino decoder 524 and the senseamplifiers 526. The latency timeout signal 566 is coupled to andtriggers the latency counter one shot circuit 578 to output a latencytimeout one shot signal 580. The latency timeout one shot signal 580triggers the address latch circuit 588 to switch the domino decoder 524to select the second set of data words/bitlines 520 by inverting thedata value for address line A4 it couples to the domino decoder 524. Thelatency timeout one shot signal 580 also triggers the sense amplifierenable circuit 554 to output a second active sense amplifier enablesignal 556. The second active sense amplifier enable signal 556initiates reading of the second set of data words/bitlines 516 that havebeen selected and coupled to the sense amplifiers 526 by the dominodecoder 524 and Y-pass multiplexers 520.

FIG. 6 shows a waveform diagram 600 of a 16 data word burst readoperation with the Flash memory 500 detailed in FIG. 5. In the waveformdiagram 600, a data request is received at the memory device 500 thataccesses a selected memory row and page. The memory burst begins at dataword 4 of the selected 16 data word column page and continues until dataword 3. In FIG. 6, the data read request is received at the memorydevice on the address inputs (not shown) and is latched in by a signalon the active low address valid input (ADVpad*) 602. The active signalon the address valid input 602 in turn generates the address valid latch(ADVL) 606 and the address valid latch one shot (ADVLOS) 608 signals.The generation of the ADVL 606 signal latches in the address inputvalues into the address latches 506, 588 and generates row and columnselect signals (not shown) and the 16 data word page select (16WPS)signal from the page decoder circuit 546, selecting the memory cells andcoupling their bitlines 518, 516 to the Y-Pass multiplexers 520. Withthe latched lower 4-bit address (A1-A4) in the address latch circuit588, the domino decoder 524 selects the data words/bitlines 516 tocouple from the Y-Pass multiplexers 520 to the inputs of the senseamplifiers 526. The generation of the ADVLOS 608 signal also generatesthe initial sense amplifier enable signal 610 from the sense amplifierenable circuit 554, causing the sense amplifiers 526 to begin sensingthe data values that have been coupled to them. At the expiration of thelatency counter 560, after 7 clock 604 periods, the latency timeout (LT)signal 614 becomes active. After a selected delay, the sense amplifierenable circuit 554 inactivates the initial sense amplifier enable signal610, which triggers the sense amplifier enable one shot 650. This causesthe intermediate latch control circuit 590 to clock/trigger 652 all ofthe intermediate latches 528 to latch the first set of data words sensedby the sense amplifiers 526.

The latency timeout signal 614 activates the 3-bit address counter 532and enables the 8 data word decoder 530. The 3-bit address counter 532has been pointed to decode and select the first data word 596 accordingto the value of address (A1-A3) first latched into the address latchcircuit 588. The latched address values, “011”, address data word 4 ofthe first sensed data word set of the selected column page and causesthe 8 data word decoder 530 to output read word select 4 (RW4) 616,which couples the output of intermediate latches 528 for data word 4 tothe data input/output buffer 534. This allows data word 4 to be read 648from the memory device 500.

The active latency timeout signal 614 also triggers the latency timeoutone shot signal 654, which causes the address latch circuit 588 tochange the domino decoder 524 to the second selected set of datawords/bitlines 516 of the selected column page. This is accomplished bythe address latch circuit 588 changing the polarity of the A4 addressline, which is coupled to and controls the domino decoder 524. Thelatency timeout one shot signal 654 also triggers the sense amplifierenable circuit 554 to output a second sense amplifier enable pulse 656,prompting the sense amplifiers 526 to begin reading the second set ofselected data words/bitlines 516 coupled to them by the domino decoder524 and the Y-Pass multiplexers 520 while the first set of sensed datawords are read out of the memory device 500 from the intermediatelatches 528.

In the burst read operation, as subsequent clock pulses are received onthe clock signal input (CLKpad) 604, the 3-bit address counter 532 isadvanced to the next data word address. This causes the coupled 8 dataword decoder 530 to output the next subsequent read word select. The3-bit address counter 532 transitions on each subsequent clock cycle 604from the initial data word address of 4 to 8, and then rolls over/wrapsaround to begin counting from 1 again until 3 is reached. In response tothe 3-bit address counter 532, the 8 data word decoder 530 selects inturn RW4 616, RW5 618, RW6 620, RW7 622, RW8 624, RW1 626, RW2 628, andRW3 630. This causes the associated data values of the first selectedset of data words to be sequentially output 648 from the memory device500.

While the 8^(th) data word of the first set (data word 11, under RW3 630in the example of FIG. 6) is read out of the memory device 500, theintermediate latch control 590 stutter steps the intermediate latches528 to latch in the data words of the second set to be read, so as toavoid any gaps or waits states in the burst read operation. In doingthis, triggered by the first trigger signal 662 (after the 7^(th) dataword of the first set, data word 10 under control of RW2 628, is readout of the memory device 500), the intermediate latch control 590 clocks658 the intermediate latches of all but the current data word being read(data word 11, currently selected by RW3 630). After the 8^(th) dataword has been read the intermediate latch control 590, triggered by thesecond trigger signal 664, clocks 660 the intermediate latches onceagain of all but the current data word being read (data word 12,currently selected by RW4 632) to complete the latching of the seconddata word set from the sense amplifiers 526.

The second data word set is then read out of the memory device 500 undercontrol of the 3-bit address counter, which will have wrapped around tothe initial address value 4 (“011”), and corresponds to data word 12 inthe currently loaded second data word set. The 3-bit address counter 532will transition on each subsequent clock cycle 604 from the initial dataword address of 12 to 16 and then roll over to begin counting from 1again until 3 is reached. In response to its input from the 3-bitaddress counter 532, the 8 data word decoder 530 selects in turn RW4632, RW5 634, RW6 636, RW7 638, RW8 640, RW1 642, RW2 644, and RW3 646.This causes the associated data values of the second selected set ofdata words to be sequentially output 648 from the memory device 500.

When the memory device 500 reaches the highest addressed data word ofthe current column page it will roll over in the current column page toread the data words addressed before the starting data word address,unless it is configured to cross the column page boundary and the nextcolumn page is accessed for read sensing. When the memory device 500crosses over a column page boundary, the starting data word addressoffset (the original starting word address in the starting column page)is not required because of the boundary crossing, which resets theoffset to zero. This allows the 3-bit synchronous address counter 532 tobe reset to an initial starting address/offset of zero.

It is noted that the initial data word access in the above examplestarted at data word 4 of the selected column page and that otherstarting data word accesses and burst sizes are possible and willoperate in a substantially similar manner. It is also noted that burstread operations with other embodiments of the present invention based onother types of memory devices are possible and should be apparent tothose skilled in the art with the benefit of the present invention.

A domino decoder in embodiments of the present invention is, incombination with the address latch circuit, designed to select sets ofdata words to be sensed that are matched to the number of availablesense amplifiers in an increasing order given a starting address inwithin the selected column page. The sets of data words are selectedwithin the column page such that the initial set is selected starting atthe first addressed data word and includes sequentially increasingaddressed data words to create a set of data word bitlines to couple tothe available sense amplifiers. The following sets of data words areselected by the domino decoder and address latch circuit in asequentially increasing address manner, and continue within the columnpage from where the previously selected set left off. Once the end ofthe column page is reached, the address latch circuit/domino decoderwraps around in the column page and selects data words starting from thefirst data word in the column page. Once the address latchcircuit/domino decoder has wrapped around the column page boundary anyadditional sequential data word sets will be selected in a sequentiallyincreasing manner from the beginning of the column page; unless thememory device is configured to cross the column page boundary and thenext column page is accessed for read sensing.

A domino decoder 1100 as could be utilized in the embodiments of thepresent invention of FIGS. 4 and 5 is detailed in FIGS. 11A and 11B. InFIG. 11B a domino decoder 1100 containing 8 decoding cells 1102 isshown. The domino decoder 1100 combines the aspects of a decoder withadder-like carry out propagation to produce a sliding window selectionof 8 of 16 data words for a given latched starting data word address.

In operation, the inputs In1 1108 and In2 1106 of the first cell 1104 ofthe domino decoder 1100 are coupled to Vcc to input a logical one forinitial carry propagation purposes. The inputs of the address A4 in theinputs A4LRT 1110, A4LRTb 1112, A4LLT 1114, and A4LLTb 1116 select thedata word on its select line outputs, OR 1118 and OL 1120 (W1 or W9),from the upper or lower half (also referred to as the right and lefthalf) of the selected column page that the first cell 1104 will coupleto the sense amplifiers (not shown) with the Y-pass multiplexer (notshown). The first cell 1104 outputs a carry propagation on Out1 1122 andOut2 1124 that is a logical one, forces all the cells 1102 downstream ofthe first cell 1104 to select their data words in the same manner (fromthe same half of the column page) as the first cell 1104, directed bythe value of address line A4 on the inputs A4LRT 1110, A4LRTb 1112,A4LLT 1114, and A4LLTb 1116. This continues until the cell that isselected by the input 3-bit initial address/offset is reached.

A cell 1102 of the domino decoder 1100 is selected by the input of thelower 3-bit address that it is configured to match/decode to. This isaccomplished by how it is coupled to the inverted and non-inverted lower3-bit latched address lines, A1-A3 1126, (A1L, A2L, A3L, A1Lb, A2Lb, andA3Lb). The 8 cells 1102 of the domino decoder 1100 are assigned so thatonly a single cell 1102 of the 8 matches each possible address input ofthe lower 3-bits A1-A3. Once a cell 1102 of the domino decoder 1100matches its assigned 3-bit address, it outputs a carry out propagationon its Out1 1122 and Out2 1124 that is a logical zero to the inputs, In11108 and In2 1106, of the remaining cells 1102 downstream of it in thedomino decoder 1100. This logical zero on the carry out propagation1122, 1124 forces the selected cell 1102 and the remaining downstreamcells 1102 to select data words to couple to the sense amplifiers fromthe opposite half of the column page that the initial cells of thedomino decoder select based on the A4 address value. When the A4 addressvalue inverts, after the latency timeout/triggering of the intermediatelatches to capture the sensed initial set of data words, the cells ofthe domino decoder switch their outputs 1118, 1120 to select the otherdata word of the two data word set that they control. Thus the dominodecoder couples the second, not initially selected, set of data words tothe sense amplifiers to be sensed.

In FIG. 11A, a single cell 1102 of the domino decoder 1100 is detailedthat would be utilized to select between 2 data words of a set of 16,given a 4-bit starting data word address. Inputs In1 1108 and In2 1106of the cell 1102 accept the carry propagation input from the previouscell 1102 in the domino decoder 1100. The inputs In3 1128, In 4 1130,and In 5 1132 accept inputs for the logical combination of the lower3-bit address values 1126 that denote the cell's 1102 position in thedomino decoder 1100. Address inputs A4LRT 1110, A4LRTb 1112, A4LLT 1114,and A4LLTb 1116 accept inputs for the fourth, most significant, addressbit of the 4-bit starting address and selects the data word that thecell will couple to the sense amplifiers in combination with the coupledcarry inputs, In1 1108 and In2 1106. The domino decoder cell 1102 isdesigned to accept the inputs A4LRT 1110, A4LRTb 1112, A4LLT 1114, andA4LLTb 1116 from a latch circuit that will invert the value of thelatched address line A4 to read the second set of data words of theselected column page. “Carry” outputs, Out1 1122 and Out2 1124,propagate the carry to the next downstream cell 1102. Data word selectoutputs, OL 1118 and OR 1120, select one of the two data words (one eachfrom the right and left halves of the selected column page) controlledby the cell 1102 for the Y-pass multiplexers to couple to a senseamplifier group to be sensed.

Internally, the cell 1102 matches the address it has been coupled torecognize from the lower 3-bit address lines 1126 with a 3-input NANDgate 1134. If the 3-input NAND gate 1134 has not recognized the cell's1102 assigned address, it outputs a logical one. The 2-input NAND gate1136 is coupled to In1 1108 and the output of the 3-input NAND gate1134, and 2-input NAND gate 1138 is coupled to In2 1106 and 3-input NANDgate 1134. The output of 2-input NAND gate 1136 is coupled to Out1 1122through inverter 1140 and the output of 2-input NAND gate 1138 iscoupled to Out2 1124 through inverter 1142. The output of the 2-inputNAND gate 1136 through inverter 1140 is also coupled to transmissiongate 1144 and to transmission gate 1146 though inverter 1148. The outputof 2-input NAND gate 1138 through inverter 1142 is also coupled totransmission gate 1150 and to transmission gate 1152 though inverter1154. The output of transmission gate 1144 and transmission gate 1146are coupled to the data word select, OL 1118, through inverter 1156. Theoutput of transmission gate 1150 and transmission gate 1152 are coupledto the data word select, OR 1120, through inverter 1158. The operationof transmission gate 1144 and transmission gate 1146 are controlled bythe address line A4 inputs A4LLT 1114 and A4LLTb 1116 to decode theaddress line A4 and select the inverted or non-inverted carry output ofthe 2-input NAND gate 1136 and inverter 1140 to couple to the data wordselect, OL 1118, through inverter 1156. The operation of transmissiongate 1150 and transmission gate 1152 are controlled by the address lineA4 inputs A4LRTb 1112 and A4LRT 1110 to decode the address line A4 andselect the inverted or non-inverted carry output of the 2-input NANDgate 1138 and inverter 1142 to couple to the data word select, OR 1120,through inverter 1158.

In operation, if the cell 1102 has not matched its configured address(by the 3-input NAND gate 1134 outputting a logical one) the 2-inputNAND gates 1136 and 1138 will output a logic state that matches theircoupled inputs In1 1108 and In2 1106, through their respectively coupledinverters 1140 and 1142, to the carry outputs, Out1 1122 and Out2 1124.If the cell has matched its configured address, the 3-input NAND gate1134 will output a logical zero and the 2-input NAND gates 1136 and 1138and their respectively coupled inverters 1140 and 1142 will output alogical zero to the carry outputs, Out1 1122 and Out2 1124 no matterwhat the inputs from In1 1108 or In2 1106 (Out1 1122 and Out2 1124 willboth be zero for a cell which is matched to its configured address. Thedata word select output OL 1118 will output a select that is dependenton the carry output state (Out1 1122 and Out2 1124) coming from theprevious cell 1102 and will be the inverse of data word select OR 1120.The A4 address line inputs of A4LRT 1110, A4LRTb 1112, A4LLT 1114, andA4LLTb 1116 invert the original states of data word select output OL1118 and OR 1120 (due to their coupling to the transmission gates 1144,1146, 1150, 1152) when the address data latch circuit inverts thelatched state of address line A4, providing access to the second dataword controlled by the cell 1102.

FIGS. 12A and 12B detail example waveforms of the domino decoder 1100 ofFIGS. 11A and 11B. In FIG. 12A a domino decoder waveform 1200 for a4-bit address of “1100” on address lines A1-A4 is shown. During thesense amplifier enable pulse 1208, the lower 3-bit latched addresses(A1-A3) 1202 of “110” are available in inverted and non-inverted formfor coupling to the address decoder NANDs 1134 of the individual dominodecoder cells 1102. The A4 address line in a “0” state is available ininverted and non-inverted form 1204 and coupled to control the right, OR1120, and left, OL 1118, data word select outputs of the individualcells 1102 of the domino decoder 1100. The value of “110” on the lower 3address lines (A1-A3) 1202 selects the fourth cell of the domino decoderand all the cells following the fourth cell 1102 (cells 5, 6, 7, and 8).Address line input A4 being zero, expressed on A4LRT, A4LRTb, A4LLT, andA4LLTb 1204, will activate the selects for data words W4, W5, W6, W7,and W8 1206 on the right side 1120 (output right, OR) and the invertedcarry outs (Out1 1122, Out 1124) after the selected fourth cell 1102activates the selects for data words W9, W10, and W11 1206 on the leftside 1118 (output left, OL).

In FIG. 12B a domino decoder waveform 1200 for a 4-bit address where thevalue of the address line A4 is inverted to give an address of “1101”(A1-A4) is shown. In FIG. 12B, during the sense amplifier enable pulse1258, the lower 3-bit latched addresses (A1-A3) 1252 of “110” areavailable, as in FIG. 12A, in inverted and non-inverted form forcoupling to the address decoder NANDs 1134 of the individual dominodecoder cells 1102. The A4 address line in a “1” state is available ininverted and non-inverted form 1254 and coupled to control the right, OR1120, and left, OL 1118, data word select outputs of the individualcells 1102 of the domino decoder 1100 in a form that is inverted to thewaveform of FIG. 12A. The value of “110” on the lower 3 address lines(A1-A3) 1202 selects the fourth cell of the domino decoder in the samemanner as the waveform of FIG. 12A (Address lines A3-A1 1252 do notchange). However, the polarity of address line A4 is changed from thewaveform of FIG. 12A, so the polarity of the data word select outputs,OL 1118 and OR 1120, are changed (inverted from FIG. 12A). In thismanner, the domino decoder 1100 activates the data word selects for W1,W2, and W3 1256 for the right side (OR) 1120 and the data word selectsfor W12, W13, W14, W15, and W16 1256 for the left side (OL) 1118.

The domino decoder of FIGS. 11A and 11B can be used with somemodification in any column page that is divisible by a power of 2, aslong as the underlying circuitry and sense amplifiers of the memory arefast enough to match the data transfer rate, as detailed above. This canbe accomplished by increasing the number of divisions in the column pageby powers of 2 (i.e., 2N) by linearly increasing the number of outputcontrolling address inputs (N) of the most significant bits of the loweraddress and the number of data words by a power of 2 that eachindividual cell 1102 of the domino decoder 1100 decodes into from theoutput controlling address inputs (N) (for example, utilizing A4 and A3in a cell 1102 to select 1 of 4 data words assigned to the cell 1102 todecode into and couple to the sense amplifiers). Additionally, thisdecreases the number of domino decoder cells 1102 contained in thedomino decoder 1100 by half for each new control address line (A4, A3)used to decode/select data words to couple to the sense amplifiers. Eachcell must then internally increase in size to increase the number ofdata words that it controls/selects to couple to a single group of senseamplifiers.

The selected column page width may also be increased by increasing thenumber of cells 1102 in a domino decoder 1100, and increasing the sizeof the internal address NAND 1134 of each cell 1102. For example, sothat one cell of a 2X domino decoder is selected, an internal addressingNAND 1134 of X inputs accepting X lower address bits is required.

In FIGS. 9 and 10, an address latch circuit and its waveforms of anembodiment of the present invention are detailed. In FIG. 9, an addresslatch circuit 900 having 4 address inputs (A1-A4) 902, 922 is shown. Theaddress latch circuit 900 passes the address inputs 902 throughtransmission gates 904 to be latched by the address latches 908 whenthey are activated by the address valid latch signal (ADVL) 906. Theaddress latches 908 are constructed of two inverters 910 that arecoupled into a feedback loop so that they hold a state. The states heldin the address latches 908 for the lower 3-bits of the 4-bit address aremade available in inverted and non-inverted form by coupled NOR gates914 on outputs A1L, A1Lb, A2L, A2Lb, A3L, and A3Lb 912. The NOR gatescoupled to act as enabled inverters and are enabled by the senseamplifier enable signal (SAEN) 916 that is coupled through inverter 918.Address line A4 922 is coupled to a first latch 924 through atransmission gate 904. The address value of the first latch 924 isconnected to a second latch 926 through transmission gate 928 all thetime except when the latency timeout one shot signal (LTOS) 946, whichis partially coupled to the transmission gate through inverter 950, islogically high. For the first sensing cycle of 8 data words, the latchvalue of A4 is preserved at the output of latch 926. For the secondsensing cycle of 8 data words, the latency one shot signal (LTOS) 946goes high for a short period of time, which disconnects the first latch924 from the second latch 926 by disabling transmission gate 928. At thesame time, the latency one shot signal (LTOS) 946 in a logical highstate changes the polarity of the address value A4 stored in the firstlatch 924. When latency one shot signal (LTOS) 946 transitions back fromlogical high to low, the first latch 924 is reconnected to the secondlatch 926 by the enable transmission gate 928, and the inverted value ofaddress line A4 is transferred through to the output of the second latch926. The address value in the second latch 926 is coupled in invertedand non-inverted form through inverters 930, 932, and 934 to the NANDgates 936 and 942 and NOR gates 938 and 940. The NAND gates 936 and 942and NOR gates 938 and 940 are coupled to produce the cell outputcontrolling address inputs A4LRT, A4LRTb, A4LLT, and A4LLTb 944. TheNAND gates 936 and 942 and NOR gates 938 and 940 are enabled by thesense amplifier enable signal 916 and the inverted sense amplifierenable signal 916 from inverter 918.

FIG. 10 details waveforms 1000 of an example operation of the addresslatch circuit 900 of FIG. 9 are shown. In FIG. 10, the latched addressvalues of address lines A1-A3 are shown in non-inverted 1002 (A1, A2,and A3) and inverted 1006 (A1b, A2b, and A3b) form, showing a lower3-bit address of “110”. The latched address value of set control addressline A4 1008 is also shown in non-inverted (A4L) and inverted form(A4Lb), showing an initial A4 address value of “0”. In operation, theaddress latch circuit 900 receives a first sense amplifier enable activepulse 1010, and asserts address lines A1-A3 1002, 1006. The initialvalue of address line A4 1008 for the right side column page multiplexerselect of the column page in non-inverted and inverted form on A4LRT1020 and A4LRTb 1022, and the left side column page multiplexer selectof the column page in non-inverted and inverted form on A4LLT 1016 andA4LLTb 1018, respectively. This selects the half of the column page thatthe initially addressed data word is in and its following sequentialaddresses for access. Upon occurrence of the latency timeout one shot(LTOS) signal 1014 and the second sense amplifier enable signal 1012,the value of the stored A4 address line is inverted 1032, 1034. Asecond, inverted signal is output for the address line A4 1008 for theright side column page multiplexer select of the column page innon-inverted and inverted form on A4LRT 1028 and A4LRTb 1030, and theleft side column page multiplexer select of the column page innon-inverted and inverted form on A4LLT 1024 and A4LLTb 1026,respectively.

In FIGS. 7 and 8, an address latch generation circuit 700 and itswaveforms 800 of an embodiment of the present invention are detailed.The address latch circuit 700 of FIG. 7 contains a clock polaritycircuit 718 containing inverters 708 and 706 and transmission gates 710and 712 that inverts the input clock signal 702, 806 under control ofthe control register bit RCRbit6 704, 802. The input clock signal 702,806 is coupled from the clock polarity circuit 718 to the clock pulsegenerator circuit 720, where a short duration clock pulse 808 is createdby coupling the clock to both inputs of NAND gate 714 directly, andthrough 3 series coupled inverters 716. The short duration clock pulse808 of the clock pulse generator circuit 720 is coupled to a clocktransfer circuit 722. The address valid latch signal 726, 810 and RCRbit15 bit signal 728, 804 from the memory configuration register are alsocoupled to the clock transfer circuit 722. The clock one shot circuitgenerates a logical zero/low output of a one clock duration afterreceiving an address valid signal 726 and resetting to a logicalone/high output after the receiving a following short duration clockpulse 808 from the clock pulse generation circuit 720. The address validsignal 726, 810 and the output from the clock transfer circuit 722 arecoupled to a 2-input NOR gate 726. A received address valid signal 726,810 pulse 818 that sets the output latch 724 to output a logical zero atADVL* 812. The second rising edge of the CLKB signal 806 will reset theoutput latch 724 through the COS signal 808 going high 816.

In FIGS. 13 and 14, an intermediate latch circuit 1400 and the read pathfor a single 2-data word grouping 1300 of an embodiment of the presentinvention are detailed. In FIG. 13, the 2-data word read path 1300 has aset of Y-pass multiplexers 1302, 1304 to pass the bitlines of 2 datawords (W1 1302/W9 1304) of the selected column page under control of adomino decoder (not shown). A group of 16 sense amplifiers 1306 sensethe 16 bits of the coupled data word from the Y-pass multiplexers 1302,1304 when enabled by the sense amplifier enable signal 1308. A group of16 intermediate latches 1310 latch the sensed data from the coupledsense amplifiers 1306 upon receiving a latch control signal/clock (TW1)1312, which is coupled directly and indirectly to the intermediatelatches 1310 through inverter 1314. The read select signal (RW1) 1318,directly and indirectly coupled to transmission gates 1316 throughinverter 1320, couples the latched data contained in the intermediatelatches 1310 to the data input/outputs 1322. In FIG. 14, an intermediatelatch 1310, 1400 is detailed. The intermediate latch 1310, 1400, has atransmission gate 1406 that couples the input sense amplifier output1404 to a latch circuit formed from two feedback coupled inverters 1410,1408, under control of the latch control signal/clock (TW1) 1402, 1312,which is coupled directly and indirectly to the intermediate latch 1400through inverter 1414, 1314. Output 1416 from the intermediate latch1400 is buffered through two serial coupled inverters 1412.

In FIGS. 15A and 15B, a sense amplifier enable circuit 1500 and itswaveforms 1550 of an embodiment of the present invention are detailed.The sense amplifier enable circuit 1500 produces a sense amplifierenable output pulse 1538, 1540 of a selected time period upon receivingeither a latency timeout signal one shot pulse 1544 or an address validlatch one shot pulse 1542. The sense amplifier enable output pulse 1538,1540 causes the sense amplifiers (not shown) to begin sensing thecoupled bitlines of the first and second data word sets, respectively.In FIG. 15A, the latency timeout signal one shot signal 1506 and addressvalid latch one shot signal 1504 are coupled to a 2-input NOR gatethrough transmission gates 1526 and 1524, respectively, of the inputcontrol circuit 1502. The output of the 2-input NOR gate 1520 of theinput circuit 1502 is coupled through an inverter 1522 to place alogical one on an input of a 2-input NAND gate 1508 and the input of aninverting capacitive delay line 1546. The inverting capacitive delayline 1546 contains a series of coupled inverters 1510 and capacitiveloads 1512, and produces a selected signal delay. The output of thecapacitive delay line 1546 is coupled to the remaining input of the2-input NAND gate 1508. The logical one output of the NOR gate 1520 andthe initial logical one output of the capacitive delay chain 1546produce a logical zero output on the NAND gate 1508. This logical zerooutput is coupled through an inverter 1514 to produce the senseamplifier enable signal 1530, 1536. The output of the NAND gate 1508 andthe output inverter 1514 are coupled back 1516, 1518 to disable theinput transmission gates 1524 and 1526. Additionally, the output of theNAND gate 1508 is coupled to pull up PMOS transistors 1528, which pullthe inputs of the 2-input NOR gate up to a logical one and latch theinput state of the sense amplifier enable circuit 1500 to active. Whenthe logical one placed on the input of the inverting capacitive delaychain 1546 propagates through, a logical zero is placed on the input ofthe NAND gate 1508. This changes the output of the NAND gate 1508 to alogical one, ending the sense amplifier enable pulse 1538, 1540 andunlocks the input circuit 1502.

In FIGS. 16A and 16B, a sense amplifier enable one shot circuit 1600 andits waveforms 1650 of an embodiment of the present invention aredetailed. The sense amplifier enable one shot circuit 1600 produces asense amplifier enable one shot pulse 1602 after the first senseamplifier enable pulse 1604 and the beginning of sensing of the firstdata word set. In FIG. 16A, the sense amplifier enable signal 1608 andlatency timeout signal 1610 are coupled to 2 inputs of a 3-input NORgate 1620. The sense amplifier enable signal 1608 is also coupled to aninverting capacitive delay chain 1606 having inverters 1616 and acapacitive load 1618. The output of the capacitive delay chain 1606 iscoupled to the remaining input of the 3-input NOR gate 1620. While thelatency timeout signal 1610 is logical zero/low, the NOR gate 1620 willproduce a short output pulse 1602 through the series coupled inverters1622 and 1624. This short output pulse 1602 is produced when the senseamplifier enable 1608 signal returns to logical zero/low 1604. The shortoutput pulse 1602 is equal to the propagation delay of the capacitivedelay chain 1606, and ends when the sense amplifier signal transition1604 propagates through the capacitive delay circuit 1606 to place alogical one on its input of the NOR gate 1620. While the latency timeoutsignal 1610 is logical one/high 1614, the NOR gate 1620 will not respondto transitions on the sense amplifier enable signal line 1608.

In FIGS. 17A and 17B, an intermediate latch control circuit 1700 and itswaveforms 1750 of an embodiment of the present invention are detailed.In FIG. 17A, a sequence of 8 intermediate latch data word group triggersignals/clocks 1716 are output by 8 2-input NAND gates 1702 coupledthrough inverters 1704. The 2-input NAND gates are triggered by a3-input NOR gate 1712 coupled to one of their inputs through an inverter1714. Three triggering event signals, consisting of the sense amplifierenable one shot signal 1710, the first trigger signal 1708, and secondtrigger signal 1706, are coupled to the inputs of the 3-input NOR gate1712 and initiate operation of the intermediate latch control circuit1700 upon receiving any one of the triggering event signals 1706, 1708,and 1710. The data word currently being read is coupled to theintermediate latch control circuit 1700 by 8 read data word selectsignals 1720. The 8 read word select signals 1720 are each coupled to asingle corresponding input of 8 2-input NAND gates 1702 throughinverters 1718. The 8 read word select signals disable the triggersignal/clock to the corresponding intermediate data latch if its data iscurrently being read from the memory.

FIG. 17B shows the waveforms of an example of operation of theintermediate latch control circuit 1700 of FIG. 17A, including a stutteraccess to avoid gaps/wait states in the data burst. In FIG. 17B, a senseamplifier enable one shot signal 1722 initiates a triggering/clocking ofthe intermediate latches 1724 after the first set of data word of acolumn page have been sensed. Because no data word is being accessed forreading, all of the intermediate data latches are clocked. A firsttrigger signal 1726 initiates a triggering/clocking 1728 of 7 of the 8groups of intermediate latches after the first 7 data words have beenread from the memory. All intermediate data latches except the datalatches of data word 3 1734, which is being selected for reading by RW31738, are clocked. A second trigger signal 1730 one clock laterinitiates triggering/clocking 1732 of 7 of the 8 groups of intermediatelatches again. All intermediate data latches except the data latches ofdata word 4 1736, which is selected for reading by RW4 1740, areclocked, finishing the filling of the intermediate latches with datafrom the second data set of the column page started by the first trigger1726.

It is noted that burst read operations with other embodiments of thepresent invention are possible and should be apparent to those skilledin the art with the benefit of the present invention.

CONCLUSION

Memory device has been described that utilizes a reduced number of senseamplifiers to sense the data bits of the selected column page. This isaccomplished by multiplexing the sense amplifiers and latching theresults to allow the sense amplifiers to sense the next set of datalines from the selected column page. The reduced number of senseamplifiers allows for a smaller internal data bus to be utilized, savingadditional circuit space and routing resources. The number of senseamplifiers are chosen such that the resulting number of data words theyread are equal to or greater than the greatest number of data words thatcan be read from the memory device in the time of the minimum readlatency time/sensing cycle time of the sense amplifiers. This allows thememory to be able to sense the next set of data bit lines and assemblethe data words before they are required to be available for reading outof the memory device. A specialized decoder, referred to herein as adomino decoder, and a latch control circuit are utilized to select a setof data bit lines to be sensed and control the data latches. This allowsthere to be no gaps or latencies while reading data from the memory dueto reloading the read latches or in multiplexing the sense amplifiers tosense a following set of data bit lines in the selected column page.Additionally, this allows a burst read starting point to be selected atrandom from the selected column page.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

1. A decoder circuit, comprising: an address input having a controladdress and an offset address; a plurality of cells having a carry inputand a carry output, wherein each cell is adapted to activate with aselected offset address and to decode a selected group of data wordsutilizing a coupled control address, where the carry input of each cellis coupled the carry output of a lower addressed previous cell of theplurality of cells, and where each data word in the group of data wordsis from a separate data word set of a plurality of data word sets of acolumn page; wherein the carry input of a first cell is coupled to afirst logic state; wherein each cell is adapted to decode an inputcontrol address and select a data word of its assigned group of datawords from a first data word set upon receiving a first logic state onits carry input; wherein each cell is adapted to decode an input controladdress and select a data word of its assigned group of data words froma second data word set upon receiving a second logic state on its carryinput; and wherein each cell is adapted to select a data word of itsassigned group of data words from a second data word set and invert thestate of the input carry from logical first state to logical secondstate on its carry output upon matching its assigned input offsetaddress.
 2. The decoder circuit of claim 1, wherein the number of cellsin the decoder circuit is
 8. 3. The decoder circuit of claim 1, whereinthe number of cells in the decoder circuit is 2(N-M), where 2N is thenumber of data words in the selected column page and 2M is the number ofdata word sets in the column page.
 4. The decoder circuit of claim 1,wherein the group of data words assigned to each cell is 2M, where 2M isthe number of data word sets in the column page.
 5. The decoder circuitof claim 1, wherein the group of data words assigned to each cell is 2.6. The decoder circuit of claim 1, wherein the number of control addresslines is M, where 2M is the number of data word sets in the column page.7. The decoder circuit of claim 1, wherein the number of offset addresslines is 2(N-M), where 2N is the number of data words in the selectedcolumn page and 2M is the number of data word sets in the column page.8. A decoder circuit, comprising: a means for inputting an addresshaving a control address and an offset address; and a means for decodingthe control address and offset address to select a first and second setof data words from a plurality of data word sets of a column page. 9.The decoder circuit of claim 8, wherein the decoder circuit has a meansfor selecting the first set of data words or the second set of datawords in response to a signal.
 10. The decoder circuit of claim 8,further comprising: a plurality of cells having a carry input and acarry output, wherein each cell contains a means for activating with aselected offset address and decoding a selected group of data wordsutilizing the coupled control address, where the carry input of eachcell is coupled the carry output of a lower addressed previous cell ofthe plurality of cells, and where each data word in the group of datawords is from a separate data word set of a plurality of data word setsof the column page; wherein the carry input of a first cell is coupledto a means for setting a first logic state; wherein each cell contains ameans for decoding an input control address and selecting a data word ofits assigned group of data words from a first data word set uponreceiving a first logic state on its carry input; wherein each cellcontains a means for decoding an input control address and selecting adata word of its assigned group of data words from a second data wordset upon receiving a second logic state on its carry input; and whereineach cell contains a means for selecting a data word of its assignedgroup of data words from a second data word set and inverting the stateof the input carry from logical first state to logical second state onits carry output upon matching its assigned input offset address. 11.The decoder circuit of claim 10, wherein the number of cells in thedecoder circuit is
 8. 12. The decoder circuit of claim 10, wherein thenumber of cells in the decoder circuit is 2(N-M), where 2N is the numberof data words in the selected column page and 2M is the number of dataword sets in the column page.
 13. The decoder circuit of claim 10,wherein the group of data words assigned to each cell is 2M, where 2M isthe number of data word sets in the column page.
 14. The decoder circuitof claim 10, wherein the group of data words assigned to each cell is 2.15. The decoder circuit of claim 10, wherein the number of controladdress lines is M, where 2M is the number of data word sets in thecolumn page.
 16. The decoder circuit of claim 10, wherein the number ofoffset address lines is 2(N-M), where 2N is the number of data words inthe selected column page and 2M is the number of data word sets in thecolumn page.
 17. A decoder circuit, comprising: an address input havinga control address and an offset address; and a decoding circuit, whereinthe decoding circuit is adapted to decode the control address and offsetaddress to select a first and second set of data words from a pluralityof data word sets of a column page.
 18. The decoder circuit of claim 17,wherein the decoder circuit is adapted to select the first set of datawords or the second set of data words in response to a control signal.19. The decoder circuit of claim 17, further comprising: a plurality ofcells having a carry input and a carry output, wherein each cell isadapted to activate with a selected offset address and to decode aselected group of data words utilizing a coupled control address, wherethe carry input of each cell is coupled the carry output of a loweraddressed previous cell of the plurality of cells, and where each dataword in the group of data words is from a separate data word set of aplurality of data word sets of a column page; wherein the carry input ofa first cell is coupled to a first logic state; wherein each cell isadapted to decode an input control address and select a data word of itsassigned group of data words from a first data word set upon receiving afirst logic state on its carry input; wherein each cell is adapted todecode an input control address and select a data word of its assignedgroup of data words from a second data word set upon receiving a secondlogic state on its carry input; and wherein each cell is adapted toselect a data word of its assigned group of data words from a seconddata word set and invert the state of the input carry from logical firststate to logical second state on its carry output upon matching itsassigned input offset address.